Advantech MIC-5332 Manual de usuario descargar pdf (Pagina 89)

Table 5.11 South Bridge Configuration

Figure 5.18 South Bridge Configuration

Disable SCU devices Disabled Enable/Disable Patsburg SCU Devices.

Onboard SAS Oprom Disabled

Enable/Disable onboard SAS Option rom if

Launch Storage OpROM is enabled.

Onboard SATA RAID Opr Enabled

Enable/Disable onboard SATA RAID Option rom

if Launch Storage OpROM is enabled.

High Precision Timer Enabled Enable/Disable the High Precision Event Timer.

USB Configuration Submenu Advanced USB Configuration

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 128 129

Revision History 2
Copyright 3
Acknowledgements 3
Product Warranty (2 years) 3
Declaration of Conformity 4
Warnings, Cautions and Notes 5
Document Feedback 5
Packing List 5
Safety Instructions 6
We Appreciate Your Input 6
Glossary 8
Chapter 1 10
Product Overview 10
1.1 MIC-5332 Overview 11
1.2 Block Diagram 13
1.3 Product Configurations 14
1.4 Related Products 14
Chapter 2 15
Board Features 15
2.1 Technical Data 16
2.2 Product Features 17
2.2.3 DMI Gen2 18
2.2.5 Redundant BIOS Flash 19
2.3 DDR3 DIMMs 20
2.3.2 RAS Mode 21
2.4 Ethernet Interface 22
2.4.2 Fabric Interface 23
2.4.3 I/O Ethernet Interface 23
2.5 Zone 3 Interface (RTM) 24
Chapter 3 26
Installation 26
3.1 Processor 27
3.2 Memory 27
3.3 Console Terminal Setup 28
3.3.2 Terminal Emulator 32
3.3.3 PuTTY Configuration 33
3.4 Installing the MIC-5332 35
3.4.2 FMM (Option) 36
3.4.3 RTM (Optional) 39
3.4.4 Storage (Optional) 39
3.4.5 Front Panel 39
3.4.6 LED Definition 40
3.4.7 Jumper Settings 42
JP5 JP6 43
Chapter 4 44
Hardware Management 44
4.1 Overview 45
4.3 Board Information 48
4.3 Sensors 50
4.3.1 Voltage Sensors 52
4.3.2 Thermal Sensors 53
4.3.3 Discrete sensors 55
4.3.4 Integrity Sensor 56
4.4 Watchdog Timers 57
4.5 E-Keying 58
4.6 Serial-over-LAN (SoL) 58
4.6.2 SoL Preparation 59
4.6.3 SoL Establishment 61
4.7 Dynamic Power Budgeting 66
4.8 MAC Address Mirroring 67
4.9 RTC Synchronization 68
Chapter 5 70
AMI APTIO BIOS Setup 70
5.1 Introduction 71
5.2 Entering Setup 71
5.3 Main Setup 72
5.4.1 PCI Subsystem Settings 75
5.4.4 WHEA Configuration 77
5.4.5 CPU Configuration 78
5.4.6 Runtime Error Logging 79
Start Unit command 82
will take before it 82
5.4.12 Network Stack 84
5.4.13 iSCSI 85
5.5 Chipset Setup 86
5.5.1 North Bridge 87
5.5.2 South Bridge 88
5.7 Boot Setup 91
5.8 Security Setup 92
5.9 Save & Exit Option 93
Chapter 6 95
Firmware Upgrade 95
6.2 IPMItool 96
6.3 BMC Upgrade 96
6.4 FPGA Upgrade 98
6.4.3 Payload Reset 100
6.5 BIOS Upgrade 101
6.5.1 Upload new BIOS image 102
6.5.3 Payload Reset 103
6.6 NVRAM Upgrade 104
<section> 105
6.6.2 Upload new NVRAM image 106
6.6.4 Payload Reset 107
Appendix A 108
39 28 00 114
39 28 00 <setting> 114
39 28 00 <POST Code> 117
39 28 00 <MAC-Address> 118
Appendix B 119
Appendix C 121
Appendix D 124
Zone 3 J32 pin out 125
Zone 3 J34 pin out 125
Appendix E 127

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