Advantech MIC-5332 Manual de usuario descargar pdf (Pagina 57)

BIOS Update Successful 0x03 0x00

Update Timeout 0x03 0x04

Update Aborted 0x03 0x02

Flash 0 boot Failed 0x03 0x29

Flash 1 boot Failed 0x03 0x31

IPMC FRU Common header CKS Error 0x08 0x3B

Internal area CKS Error 0x08 0x43

Chassis info area CKS Error 0x08 0x4B

Board info area CKS Error 0x08 0x53

Product info area CKS Error 0x08 0x5B

Multi record area CKS Error 0x08 0x63

RTC Time sync with ShMM Successful 0x09 0x68

Time sync with ShMM Failed 0x09 0x69

Table 4.8 Integrity Sensor List

For example, below is a SEL entry generated by the integrity sensor:

By referring to Table 4.8, Integrity Sensor List, this event can be interpreted as: the

RTC has been successfully synced with the ShMM.

4.4 Watchdog Timers

Two kinds of watchdog timers are built into the IPMC. One is used to supervise the

IPMC firmware (IPMC watchdog), and the other is used to supervise the x86 payload

(BMC watchdog). When the IPMC is firmware is stuck, the IPMC watchdog bites and

resets the IPMC. The payload is not affected from this watchdog event.

The BMC Watchdog of the MIC-5332 IPMC is used for:

 BIOS Power On Self Test (POST) watchdog

 OS load watchdog

 Application level watchdog (user application dependent)

After Payload power on, the BMC Watchdog will monitor the BIOS POST process and

will bite in case the BIOS fails. When the watchdog bites, the payload will be reset and

the IPMC selects the other BIOS image to boot. Once BIOS POST is finished

successfully, the BMC watchdog timer is disabled (before the OS boot loader starts).

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 128 129

Sin comentarios

Advantech MIC-5332 Manual de usuario Pagina 57