
Mirrored Channel Mode
In Mirrored Channel Mode, the memory contents are mirrored between Channel
0 and Channel 2 and also between Channel 1 and Channel 3. As a result of the
mirroring, the total physical memory available to the system is half of what is
populated. Mirrored Channel Mode requires that Channel 0 and Channel 2, and
Channel 1 and Channel 3 must be populated identically with regards to size and
organization. DIMM slot populations within a channel do not have to be identical
but the same DIMM slot location across Channel 0 and Channel 2 and across
Channel 1 and Channel 3 must be populated the same.
Lockstep Channel Mode
In Lockstep Channel Mode, each memory access is a 128-bit data access that
spans Channel 0 and Channel 1 and Channel 2 and Channel 3. Lockstep
Channel mode is the only RAS mode that allows SDDC for x8 devices. Lockstep
Channel Mode requires that Channel 0 and Channel 1, and Channel 2 and
Channel 3 must be populated identically with regards to size and organization.
DIMM slot populations within a channel do not have to be identical but the same
DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and
Channel 3 must be populated identically.
3. Note:
The memory channel mode can be configured in BIOS setup menu described in Chapter
5, AMI BIOS Setup.
Regarding the correct installation of memory modules, please refer to Section 3.2,
Memory for further details.
2.4 Ethernet Interface
2.4.1 Base Interface
The MIC-5332 uses Intel® i350-AM4 LAN controller, connected to the Intel® Xeon®
E5-2600 series Processor (CPU0) through a PCIe x4 interface to provide dual GbE
ports for the Base Interface.
The Intel® Ethernet Controller I350 is a single, compact, low power component that
supports quad port and dual port gigabit Ethernet designs. The device offers four
fully-integrated gigabit Ethernet media access control (MAC), physical layer (PHY)
ports and four SGMII/SerDes ports that can be connected to an external PHY. The
I350 supports PCI Express* (PCIe v2.1 (2.5GT/s and 5GT/s)).
The device enables two-port or four port 1000BASE-T implementations using
integrated PHY’s.
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