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Advantech SOM-Express Design Guide
66 Chapter 5 Carrier Board Design Guidelines
5.7.2.3 Implementation of indicators
Some RJ-45 include LEDs which need 3.3 volts to drive the link and action LEDs, so
we need to provide 3.3 volts on the carrier board. Link and activity LEDs can be
implemented by using the SOM-Express module’s GBE0_ACT#, GBE0_LINK#,
GBE0_LINK100#, and GBE0_LINK1000# pins. These pin’s sink current is intended
for attachment to a LED cathode. The anode of the LED should be pulled to 3.3 volts
through a resistor of 220 # or greater.
5.7.3 Layout Guidelines
Critical signal traces should be kept as short as possible to decrease the likelihood of
being affected by high frequency noise from other signals; including noise carried on
power and ground planes. Keeping the traces as short as possible can also reduce
capacitive loading.
Designing for gigabit operation is very similar to designing for 10/100 Mbps.
10/100Mbps has two differential pairs, but can be generalize for a gigabit system with
four analog pairs.
5.7.3.1 Differential pairs design considerations
! Maintain constant symmetry and spacing between the traces within a differential
pair. Keep the signal trace lengths of a differential pair equal to each other. Do
not use serpentines to try to match trace lengths in the differential pair.
Serpentines cause impedance variations causing signal reflections, which can be
a source of signal distortion. Try to keep the length difference of the differential
pair less than 100 mil (~15 pS). Always go straight to the required via or pad.
! The total length of each differential pair should be less than 4 inches. There is 1.5
inches on SOM-Express, so keep the length of each differential pair under 2.5
inches. Figure 5-30 shows an example. L1 is 1.5 inches on the SOM-Express. On
your carrier board, L2 should be less than 2.5 inches.
! Do not route the transmit differential traces closer than 100 mils to the receive
differential traces for 10/100 Mbps.
! Do not route any other signal traces (including other differential pairs) parallel to
the differential traces or closer than 100 mils to the differential traces. Figure 5-30
shows an example. We recommend length L3 to be kept longer than 100 mils.
! Separate traces within a differential pair as small as possible down to 5 to 8
mils. Close separation of the traces allow the traces to couple well to each other.
! For high-speed signals, it should minimize the number of corners and vias. If a
90° bend is required, it is recommended to use two 45° bends instead. Please
see Figure 5-31 for an example.
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
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