Advantech MMP3-21 Manual de usuario descargar pdf (Pagina 5)

Advantech SOM-Express Design Guide

Table of Contents 5

Figure 5-10 Violation of Proper Routing Techniques....................50

Figure 5-11 Creating Unnecessary Stubs....................................50

5.3 AC Link/Azalia interface ........................................................................51

5.3.1 Signal Description.........................................................................51

Table 5.10 Audio signals description............................................51

5.3.2 Design Guidelines.........................................................................51

Figure 5-12 AC link Connections..................................................52

Figure 5-13 Azalia link Connections .............................................52

Figure 5-14 AC link Audio Layout Guidelines...............................53

Figure 5-15 Sense resistor examples...........................................53

5.3.3 Layout Guidelines.........................................................................54

Figure 5-16 Azalia – AC_SDIN Topology .....................................54

Table 5.11 Azalia – AC_SDIN Routing Summary.........................54

Figure 5-17 Azalia –

AC_SDOUT/AC_SYNC/AC_BITCLK/AC_RST# Topology#1.......

Table 5.12 Azalia – AC_SDOUT/AC_SYNC/AC_

BITCLK/AC_RST# Topology #1 ...................................................

Figure 5-18 Azalia –

AC_SDOUT/AC_SYNC/AC_BITCLK/AC_RST# Topology#2.......

Table 5.13 Azalia – AC_SDOUT/AC_SYNC/AC_

BITCLK/AC_RST# Topology #2 ...................................................

5.4 VGA .......................................................................................................56

5.4.1 Signal Description.........................................................................56

Table 5.14 VGA signals description..............................................56

5.4.2 Design Guidelines.........................................................................57

Figure 5-19 VGA Connections......................................................57

5.4.3 Layout Guideline...........................................................................57

Figure 5-20 VGA Layout Guidelines .............................................57

Figure 5-21 RGB Output Layout Guidelines .................................58

5.5 LVDS .....................................................................................................59

5.5.1 Signal Description.........................................................................59

Table 5-15 LVDS signals description...........................................59

5.5.2 Design Guideline ..........................................................................59

Figure 5-22 LVDS LCD Connections............................................59

Table 5-16 LVDS Signals Trace Length Mismatch Mapping ........60

5.5.3 Layout Requirements....................................................................60

Figure 5-23 LVDS Signal Routing Topology.................................60

5.6 Primary IDE0 .........................................................................................61

5.6.1 Signal Description.........................................................................61

Table 5-17 IDE signals description..............................................61

5.6.2 Design Guidelines.........................................................................61

Figure 5-24 IDE Master/Slave Handshake Signals Connection ...62

Figure 5-25 IDE Bus Trace on Carrier Board and Cable ..............62

Figure 5-26 IDE0 Connections .....................................................63

5.6.3 Layout Guidelines.........................................................................63

Table 5-18 IDE Routing Summary................................................63

5.7 Ethernet.................................................................................................64

5.7.1 Signal Descriptions.......................................................................64

Table 5-19 Ethernet signal description .........................................64

5.7.2 Design Guidelines.........................................................................64

Figure 5-27 10/100M Ethernet Connections.................................65

Figure 5-28 Gigabit Ethernet Connections ...................................65

Figure 5-29 Ground Plane Separation..........................................65

5.7.3 Layout Guidelines.........................................................................66

Figure 5-30 Differential signals route example .............................67

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