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Advantech SOM-Express Design Guide
64 Chapter 5 Carrier Board Design Guidelines
5.7 Ethernet
SOM-Express supports the IEEE802.3 network interface and flexible dynamically
loadable EEPROM algorithm. The network interface complies with the IEEE standard
for 10BASE-T, 100BASE-T and 1000BASE-T Ethernet interfaces.
5.7.1 Signal Descriptions
Table 5-19 shows SOM-Express Ethernet signals, including pin number, signals, I/0,
power plane and descriptions.
Table 5-19 Ethernet signal description
Pin Signal I/O Description
A13,A9,A7,A3
A12,A10,A6,A2
GBE0_MDI[0:3]+
GBE0_MDI[0:3]-
I/O Gigabit Ethernet Controller 0: Media Dependent Interface
Differential Pairs 0,1,2,3. The MDI can operate in 1000,
100 and 10 Mbit / sec modes. Some pairs are unused in
some mode, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
B2 GBE0_ACT# OD Gigabit Ethernet Controller 0 activity indicator, active low.
A8 GBE0_LINK# OD Gigabit Ethernet Controller 0 link indicator, active low.
A4 GBE0_LINK100# OD Gigabit Ethernet Controller 0 100 Mbit / sec link indictor,
active low.
A5 GBE0_LINK1000# OD Gigabit Ethernet Controller 0 1000 Mbit / sec link indictor,
active low.
A14 GBE0_CTREF REF Reference voltage for Carrier board Ethernet channel 0
magnetics center tap. The reference voltage is determined
by the requirements of the module PHY and may be as
low as 0 V and as high as 3.3 V.
The reference voltage output shall be current limited on
the module. In the case in which the reference is shorted
to ground, the current shall be limited to 250 mA or less.
5.7.2 Design Guidelines
5.7.2.1 Differential Pairs
Route the transmit and receive lines on the input (SOM-Express module) side of the
coupling transformer on the carrier board PCB as differential pairs, with a differential
impedance of 100 #. PCB layout software allows determination of the correct trace
width and spacing to achieve this impedance after the PCB stack-up configuration is
known.
With 10/100M, the TX+, TX- signal pair should be well separated from the RX+, RX-
signal pair. Both pairs should be well separated from any other signals on the PCB.
The total routing length of these pairs from the SOM-Express module to the Ethernet
jack should be made as short as practical. If the carrier board layout doesn’t specify
where the Ethernet jack is located, it should be placed close to the SOM-Express
module pins.
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
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