
33 PCI-1706U User Manual
Appendix A Specifications
A.3 Analog Output
A.4 Digital Input/Output
External Clock
Logic level TTL (Low: 0.8 V max. High: 2.0V min.)
Input impedance Hi Z
Input coupled DC
Frequency Up to 10MHz(Max 250k for use)
External Trigger
Logic level TTL (Low: 0.8 V max. High: 2.0V min.)
Input impedance Hi Z
Input coupled DC
External Analog
Trigger Input
Range By analog input range
Resolution 8-bit
Frequency Up to 150kHz
Channels 2
Resolution 12-bit
Output Range
(Internal Reference)
Voltage 0 ~ +10 V, 0 ~ +5 V -5V ~ +5 V -10 V ~ +10 V
Current 0 ~ 20 mA, 0 ~ 24 mA, 4 ~ 20 mA
Accuracy
DNLE
±1LSB
INLE
±1LSB
Gain Error Adjustable to zero (DC Output)
Slew Rate
1V/
µs, 2mA/µs
Drift 40ppm/°C (Voltage) 70ppm/°C (Current)
Driving Capability 5 mA (Voltage), 5 V (Current)
Max. Update Rate 30K samples /s
Output Impedance 3 Ohm (max)
Settling Time
30
µs (Voltage) / 40 µs (Current) ( to ±1/2 LSB of FSR)
Channels 16
Input Voltage
Low 0.4 V max.
High 2.4 V min.
Input Load
Low 0.4 V max. @ -0.2mA
High
2.7 V min. @ 20
µA
Output Voltage
Low 0.4 V max. @ + 8.0 mA (sink)
High 2.4 V min. @ -0.4 mA (source)
Comentarios a estos manuales