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18 PCL-740 User's Manual

This appendix gives short description of each of the module's regis-

ters. For more information please refer to the data book for the

STARTECH 16C550 UART chip.

All registers are one byte. Bit 0 is the least significant bit, and bit 7 is

the most significant bit. The address of each register is specified as an

offset from the port base address (BASE), selected with DIP switch

SW1 or SW2.

DLAB is the "Divisor Latch Access Bit", bit 7 of BASE+3.

BASE+0 Receiver buffer register when DLAB=0 and the opera-

tion is a read.

BASE+0 Transmitter holding register when DLAB=0 and the

operation is a write.

BASE+0 Divisor latch bits 0 - 7 when DLAB=1.

BASE+1 Divisor latch bits 8 - 15 when DLAB=1.

The two bytes BASE+0 and BASE+1 together form a 16-bit number,

the divisor, which determines the baud rate. Set the divisor as follows:

Baud rate Divisor Baud rate Divisor

50 2304 2400 48

75 1536 3600 32

110 1047 4800 24

133.5 857 7200 16

150 768 9600 12

300 384 19200 6

600 192 38400 3

1200 96 56000 2

1800 64 115200 1

2000 58

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29

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Advantech PCL-740 Especificaciones Pagina 21